The present invention relates to semiconductor devices and manufacturing techniques thereof, and more specifically, to a technique effectively applied to a semiconductor device with a semiconductor chip mounted over a wiring substrate, and assembly of the semiconductor device.
Japanese Patent Publication No. 4942020 (Patent Document 1) discloses a stacked structure including a laminate of two semiconductor chips accommodated in one package. Specifically, the two semiconductor chips are stacked on each other over a module substrate, and respectively coupled to bonding leads on the module substrate via wires.
Further, Japanese Unexamined Patent Publication No. 2000-294684 (Patent Document 2) discloses a structure including a semiconductor chip mounted at the center of a surface of a quadrilateral package base. A plurality of bonding leads is arranged in two lines at the periphery of the center on the same plane of the package base.